Vikas Mishra

2005-08-16 07:01:01 UTC

Hi Folks,

We were having a discussion today about having a "non power of 2

instruction cache". Conceptually I would think that the only "hard"

reason for having a power of 2 is that the line index calculation is

trivial and for a non power of 2 it would be some complicated

calculation like modulus with 40K (for a size of say 40KB) or something

equally strange.

But is there any other real reason besides this why "non power of 2

caches" can't be used ? I seemed to remember having read somewhere that

cache's can't be non power of two but I don't remember where. I have

searched Hennessey and Patterson ( "A Quantitative Approach" ) but

wasn't able to find anything specific which said whether this is

possible or not.

In case there have been real/experimental designs with non power of 2

caches, could you point me to references.

Thanks & Regards,

Vikas

We were having a discussion today about having a "non power of 2

instruction cache". Conceptually I would think that the only "hard"

reason for having a power of 2 is that the line index calculation is

trivial and for a non power of 2 it would be some complicated

calculation like modulus with 40K (for a size of say 40KB) or something

equally strange.

But is there any other real reason besides this why "non power of 2

caches" can't be used ? I seemed to remember having read somewhere that

cache's can't be non power of two but I don't remember where. I have

searched Hennessey and Patterson ( "A Quantitative Approach" ) but

wasn't able to find anything specific which said whether this is

possible or not.

In case there have been real/experimental designs with non power of 2

caches, could you point me to references.

Thanks & Regards,

Vikas